The present invention generally relates to fabrication of semiconductor devices and more particularly to a fabrication method of a semiconductor device including a polishing step, as well as to a slurry used for such a polishing step.
In semiconductor integrated circuits, a multilayer interconnection structure is used commonly for achieving electric interconnection between various semiconductor devices formed on a common semiconductor substrate. A multilayer interconnection structure generally includes an insulation layer provided on the semiconductor substrate and a wiring pattern embedded in such an insulation layer. As such a multilayer interconnection structure includes a plurality of interconnection layers stacked with each other, it is necessary that each interconnection layer has a flat upper major surface for allowing such a stacking of the interconnection layers thereon.
Thus, it has been practiced conventionally to form such a multilayer interconnection structure by: forming a contact hole or wiring groove on an insulation layer; filling the contact hole or wiring groove by a conductor layer; and polishing the conductor layer until the surface of the insulation layer is exposed. Thereby, a flat surface is guaranteed for each of the interconnection layer, and the formation of another interconnection layer including an insulation layer and a conductor pattern embedded therein, is substantially facilitated.
FIGS.1A-1J show the process of forming such a multilayer interconnection structure including a polishing step as applied to a fabrication process of a MOS transistor.
Referring to FIG. 1A, the MOS transistor is formed on a Si substrate 1 doped to the p-type in correspondence to an active region 1A defined by a field oxide film 1a. More specifically, the MOS transistor includes a diffusion region 1b of the n.sup.+ -type formed on the surface of the active region 1A and another diffusion region 1c also of the n.sup.+ -type formed on the surface of the active region 1A, wherein the diffusion region 1b and the diffusion region 1c are separated from each other by a channel region 1d of the MOS transistor. On the substrate 1, there is provided a gate electrode 2 so as to cover the channel region 1d with an intervening gate oxide film (not shown). Further, the gate electrode 2 carries side wall insulation films 2a and 2b on respective opposing side walls. It should be noted that the diffusion regions 1b and 1c act respectively as a source and a drain of the MOS transistor.
In the step of FIG. 1A, an interlayer insulation film 3 of SiO.sub.2 is deposited by a CVD process so as to bury the MOS transistor formed as such, typically with a thickness of about 50 nm. As a result of deposition of the interlayer insulation film 3, the gate electrode 2 as well as the diffusion regions 1b and 1c are covered by the SiO.sub.2 film 3. Thereby, the interlayer insulation film 3 shows a projection and a depression in conformity with the foregoing gate electrode 2 as indicated in FIG. 1A.
Next, in the step of FIG. 1B, the structure of FIG. 1A is planarized by polishing the surface of the insulation film 3 uniformly. Further, in the step of FIG. 1C, the insulation film 3 is subjected to a photolithographic patterning process, in which a contact hole 3a is formed in the interlayer insulation film 3 so as to expose the surface of the diffusion region 1b, and a conductor layer 4 of a metal or alloy such as W, Al or Cu, is deposited in the step of FIG. 1D on the structure of FIG. 1C uniformly by a CVD process. As a result, the conductor layer 4 fills the contact hole 3a and the conductor layer 4 contacts with the diffusion region 1b at the foregoing contact hole 3a. As the conductor layer 4 fills the contact hole 3a as noted above, the conductor layer 4 shows a depression on the upper major surface thereof in correspondence to the contact hole 3a.
Next, the conductor layer 4 is polished uniformly, and a structure shown in FIG. 1E is obtained. In the structure of FIG. 1E, it should be noted that a flat surface is obtained in correspondence to the upper major surface of the insulation layer 3. Preferably, the polishing of the conductor layer 4 acts selectively to the metal forming the conductor layer 4 and stops more or less spontaneously upon exposure of the upper major surface of the insulation film 3. As a result of such a polishing, a conductive plug 4b is formed in contact with the diffusion region 1b such that the conductive plug 4b fills the contact hole 3a. As a result of the planarization, achieved by the polishing process, the conductive plug 4b has an upper major surface coincident to the upper major surface of the insulation film 3.
Next, in the step of FIG. 1F, another insulation film 5 of SiO.sub.2, and the like, is formed on the planarized structure of FIG. 1E, followed by a photolithographic patterning process, to form a groove 5a as indicated in FIG. 1G, such that the groove 5a exposes the conductive plug 4b. Further, in the step of FIG. 1H, another conductor layer 6, typically formed of a metal or alloy of W, Al, Cu, and the like, is deposited on the structure of FIG. 1G. As a result, a depression 6a is formed on the conductor layer 6 as indicated in FIG. 1H in correspondence to the groove 5a.
Further, the conductor layer 6 is polished in the step of FIG. 1I to form a planarized structure, wherein it will be noted that the groove 5a is filled by a conductor pattern 6b that forms a part of the foregoing conductor layer 6. After the structure of FIG. 1I is thus formed, another insulation film 7 is provided as indicated in FIG. 1J. Thereby, it is possible to form various interconnection patterns on the insulation film 7.
In the foregoing fabrication process, it has been practiced to carry out the polishing steps of FIG. 1E and FIG. 1I on an abrasive cloth of a urethane resin, by using a mixture of .alpha.-Al.sub.2 O.sub.3 and H.sub.2 O.sub.2 as the slurry. A typical example of the slurry is MSW-1000 (trade name) supplied from Rodel. When using such a mixture of .alpha.-Al.sub.2 O.sub.3 and H.sub.2 O.sub.2 as the slurry, H.sub.2 O.sub.2 causes an oxidation in the conductor layer to be polished, and the .alpha.-Al.sub.2 O.sub.3 abrasive particles grind away the oxides formed as a result of the oxidation of the conductor layer.
For example, the grinding of a W layer by means of the foregoing slurry first causes a formation of W.sub.x O.sub.y as a result of the oxidation by H.sub.2 O.sub.2, while the foregoing oxide (W.sub.x O.sub.y) is easily removed by the .alpha.-A1.sub.2 O.sub.3 grains.
On the other hand, the use of such a conventional slurry, which contains H.sub.2 O.sub.2, a strong liquid oxidant, causes a problem, when applied to the polishing of a conductor layer such as W or other metal, in that H.sub.2 O.sub.2 penetrates deeply into the conductor layer 4 filling the contact hole 3a along a seam 4c that is formed in the conductor layer 4 at the time of deposition of the conductor layer 4. Thereby, the polishing of the conductor layer 4, conducted under existence of H.sub.2 O.sub.2, enlarges the depression from the state of FIG. 2A to the state of FIG. 2B. In other words, there is formed a large and deep depression generally at the center of the conductive plug 4b in correspondence to the foregoing seam 4c as indicated in FIG. 2B, while such a large depression causes a problem of reliability of electrical contact at the contact hole 3a. The problem of the formation of the depression in the contact hole as a result of polishing becomes particularly serious in high density integrated circuits and semiconductor devices in which the diameter of the contact hole 3a is 0.5 .mu.m or less.
It should be noted that the foregoing seam 4c is formed as a result of abutting of the conductor layers growing from both lateral side walls of the contact hole 3a toward the center of the contact hole when the conductor layer is deposited. Because of the nature of the seam as such, the seam 4c contains a large amount of defects or imperfections and is extremely vulnerable to oxidation by H.sub.2 O.sub.2. The oxidized part of the plug 4b is easily removed by polishing using abrasive particles such as .alpha.-Al.sub.2 O.sub.3.
Further, such conventional slurries have suffered from the problem of relatively low selectivity in that the polishing does not stop exactly at the interface between an insulator layer and a conductor layer. Thereby, there is a substantial risk that the layer that should not be polished is unwantedly polished by the abrasive particles.